This invention relates to high-speed data processors (sequence operation processors) capable of processing a special operation instruction (sequence operation instruction) which is different from a normal execution instruction at high speeds.
FIG. 9 is a system configuration diagram showing an exemplary sequence operation processor which is a conventional data processor. In the figure, reference numeral 1 designates a prefetchable central processing unit (CPU); 2, a memory for storing a normal execution instruction or a sequence operation instruction that is a special operation instruction; 3, a decoder for decoding a command (an instruction) applied from the CPU 1 when the instruction read from the memory 2 is an instruction for a sequence operation; 4, a sequence operation control section for causing the sequence operation to be executed by a decode signal 5 from decoder 3 and an address and data from the CPU 1; 6, a sequence operation register; 7, a working RAM for storing the result of the sequence operation; 8, an address bus; and 9, a data bus.
FIG. 10 is an operation sequence diagram which explains the operation of the sequence operation processor shown in FIG. 9. In the figure, reference numerals 201-220 designate cycles in its operation process.
An operation of the conventional sequence operation processor shown in FIG. 9 will be described with reference to the operation sequence diagram shown in FIG. 10. An address applied from the CPU 1 through the address bus 8 reads an instruction from the memory 2, and the read instruction is received by the CPU 1. While decoding and executing the read instruction, the CPU 1, if ready to prefetch an instruction, reads a next instruction from the memory 2 and decodes it.
If the instruction decoded by the CPU 1 is an instruction for a sequence operation, the CPU 1 issues a predetermined command to the decoder 3 for the sequence operation and request for a sequence operation start. The received command causes the decoder 3 to send a target decode signal 5 to sequence operation control section 4. The sequence operation control section 4, in turn, executes the sequence operation by decoding the decode signal 5, the address in the address bus 8, and the data in data bus 9, and stores the result of the sequence operation in the working RAM 7.
Indicating such an operation over the operation sequence diagram shown in FIG. 10, cycles 201-210 designate instruction reading (FETCH, hereinafter referred to as "F") operation by the CPU 1, an instruction decoding (DECODE: hereinafter referred to as "D") operation, and an instruction executing (EXECUTE: hereinafter referred to as "E") operation; cycles 211-220, an instruction reading F operation, an instruction decoding D operation, and an instruction executing E operation by CPU 1, and a sequence operation executing E operation by the sequence operation processor.
The instruction executing cycle by the CPU 1 will now be described taking cycles 201-210 as an example. The CPU 1 reads an instruction from memory 2 at cycle 201, decodes the read instruction at the cycle 202, and executes the decoded instruction at the cycle 203. If ready to prefetch an instruction during the instruction decoding and executing cycles, the CPU 1 reads an instruction at cycle 205, decodes the read instruction at cycle 204, and executes various operations at cycle 206 when ready to execute the next instruction. If ready to prefetch another instruction again after having executed the instruction, the CPU 1 reads an instruction from the memory 2 at the cycle 208. With the above operations, the CPU 1 completes a set of instruction executing cycles.
Cycles 211-220 at which the sequence operation processor executes a sequence operation will next be described. If an instruction read by the CPU 1 at cycle 211 is decoded to be a sequence operation instruction at cycle 212, the sequence operation instruction is executed by causing the CPU 1 to apply a command, an address, and data to both decoder 3 and sequence operation control section 4 taking advantage of instruction executing cycle 213. The CPU 1, not being able to read any instruction during this sequence operation instruction execution cycle, can decode only a prefetched instruction corresponding to a number of pipelines within the CPU 1 among the prefetched instructions at cycle 214 when cycle 213 is being executed and at cycle 217 when cycle 216 is being executed.
FIG. 11 is a system configuration diagram showing another exemplary sequence operation processor which is a conventional data processor disclosed in, e.g., Published Unexamined Japanease Patent Application No. 38902/1987. In the figure, reference numeral 11 designates a prefetchable CPU; 12, a bit data arithmetic and logic unit (Bit ALU); 13, a programable read only memory (ROM); 14, a pseudo-instruction conversion circuit which, if an instruction applied from the ROM 13 is directed to the Bit ALU 12, converts the instruction to a nonexecution instruction (NOP) and applies the NOP to the CPU 11; 15, a control signal line which informs to the Bit ALU 12 that an instruction currently applied from the ROM 13 is to be directed to the Bit ALU 12, the signal line transmitting the most significant bit (MSB) of the ROM 13; 16, a first data bus for transmitting an instruction applied from the ROM 13; 17, a second data bus for transmitting data between the CPU 11 on the one hand and the pseudo-instruction conversion circuit 14, the Bit ALU 12, and RAM 18 for storing operation results on the other; 19, an external interface circuit (I/F) of a sequence control unit; and 20, an address bus.
FIGS. 12 and 13 are an instruction arrangement diagram and an operation sequence diagram which explain the operation of the sequence operation processor shown in FIG. 11. In the figures, reference numeral 501-504 designate instructions; and 501a-501c, 602a-502d, 503a-503d, 504a-504c, cycles in its operation process.
An operation of the conventional sequence operation processor shown in FIG. 11 will now be described with reference to the instruction arrangement diagram shown in FIG. 12 and the operation sequence diagram shown in FIG. 13. The CPU 11 reads a program written in the ROM 13. If the program read from the ROM 13 is not a program for operating the Bit ALU 12, i.e., a CPU instruction, the MSB of the program is "0." Even if this program is applied to both the Bit ALU 12 and the pseudo-instruction conversion circuit 14 through the control signal line 15, the Bit ALU 12 is not operated while the pseudo-instruction conversion circuit 14 transmits this program applied from the ROM 13 directly to the CPU 11 which causes the CPU 11 to decode and execute the received instruction.
If, on the other hand, the program read by the CPU 11 from the ROM 13 is to operate the Bit ALU 12, i.e., a special operation instruction, the MSB of the program is "1," and the program is applied to both the Bit ALU 12 and the pseudo-instruction conversion circuit 14 through the control signal line 15. Upon reception of the program, the Bit ALU 12 executes bit data processing over data held in the RAM 18 by an instruction (data) applied from the ROM 13. At the same time, the pseudo-instruction conversion circuit 14 converts the special operation instruction applied from the ROM 13 to a nonexecution instruction (NOP) for the CPU 11 and applies the NOP to the CPU 11. The CPU 11 then decodes and executes the NOP, and proceeds to a next cycle ignoring any external access. That is, the Bit ALU 12 can execute bit data processing while the CPU 11 is executing an instruction prefetch cycle.
Indicating the above operation over the instruction arrangement diagram shown in FIG. 12 and the operation sequence diagram shown in FIG. 13, reference numerals 501, 504 designate CPU instructions; and 502, 503, special operation instructions in FIG. 12. Describing the same operation with respect to the operation sequence diagram shown in FIG. 13, with reference to the cycles for CPU instruction 501, the CPU 11 reads an instruction from the ROM 13 at reading cycle 501a, decodes the read instruction at decoding cycle 501b, and executes the decoded instruction at executing cycle 501c. With respect to the cycles for CPU instruction 504, the cycles similar to the above will be repeated to execute the instruction.
With respect to the cycles for executing special operation instruction 502 by the Bit ALU 12, CPU 11 only reads an instruction applied from the ROM 13 and converted to NOP at cycle 502a, decodes the NOP at cycle 502b, and executes the NOP at cycle 502c, and at the same time, causes the Bit ALU 12 to execute the special operation at special operation executing cycle 502d. These operations are similarly applied to special operation instruction 503.
Since the sequence operation processor shown in FIG. 9, which is a conventional data processor, is constructed as described above, even if CPU 1 that is capable of prefetching an instruction is used to execute a sequence operation, it is after the CPU 1 has read the instruction and decoded the sequence operation instruction that the sequence operation control section 4 executes the instruction. Thus, while the instruction is being read by the CPU 1, the sequence operation control section 4 cannot execute the sequence operation instruction, thereby not allowing the CPU 1 to read an instruction when the sequence operation is being executed by the sequence operation control section 4. Thus, the sequence operation processing time is long.
In order to overcome the above problem of increased sequence operation processing time, the sequence operation processor shown in FIG. 11, which is disclosed in Published Unexamined Japanese Patent Application No. 38902/1987, has been proposed. This sequence operation processor executes a special operation, i.e., a sequence operation, only during the instruction reading cycle, eliminating the need for CPU11 to send data to the sequence operation processor in executing the special operation, thereby allowing a high-speed special operation. However, if prefetchable CPU 11 is used to improve data processing performance, the data processor executes the special operation processing for a prefetched instruction before an instruction that is currently being executed by CPU 11. As a result, if exceptional processing such as interrupt processing occurs, when the CPU 11 returns from taking care of such exceptional processing, a special operation instruction which has been prefetched but not executed as a nonexecution instruction by the CPU 11 is executed again, thereby making the operation result incorrect. Thus, the CPU 11 must not be returned immediately in such a case. In addition, if a special operation instruction is arranged after a CPU instruction within a prefetchable range, and if the CPU instruction is such an instruction that uses the result of the special operation, the result of the special operation which is to be used upon decoding the CPU instruction is the result of the special operation executed by prefetching the instruction. Thus, the succeeding instruction is unreasonably executed before the preceding instruction is executed. As a result, no special operation instruction can be arranged immediately after a CPU instruction. Thus, the instructions must be arranged in such an order: a CPU instruction, a dummy instruction, and a special operation instruction, resulting in a bulky instruction memory.